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Eureka Technology
Product Summary
EP100 PowerPC Bus Slave
FEATURES
* Fully supports PowerPCTM 60x bus protocol including PowerPC 603, 604, 740, 750 and MPC8260. * Provide PowerPC bus device access to memory and devices on user interface. * Direct support for standard asynchronous SRAM and synchronous BURST SRAM. * Burst access support using conventional asynchronous SRAM. * Additional back-end interface bus for on-chip and off-chip logic and register access. * Back-end interface supports user device with various wait states. * Burst access support including MPC8260 extended transfer size. * Write buffer supports write posting for the back-end bus interface. * Handles separate address bus and data bus tenure. * Supports PowerPC address pipeline for improve performance. * Supports address bus retry generated by other external device. * Qualified address data bus grant through the use of bus busy signals. * Designed for ASIC and programmable logic device implementations in various system environments. * Fully static design with edge triggered flip-flops. * Optimized for Actel SX-A, RTSX-S, AX, and APA product families.
PowerPC Host Bus
EP100 PowerPC Bus Slave
D0-63 D7-D0
A14-A0
A14-A0 OE WE CS
SRAM and Burst SRAM
User Logic
OE# WE# CS#
(c) 2003 by Eureka Technology Inc. 4962 El Camino Real, Los Altos, CA 94022, USA
Page 1
Tel: 1 650 960 3800 Fax: 1 650 960 3805 http://www.eurekatech.com
Eureka Technology
EP100 PowerPC Bus Slave
DESCRIPTIONS
The EP100 PowerPC bus slave device is a bus interface unit designed for the PowerPC host bus. It is designed to work on any 60x compliant bus architecture. It has two user interfaces, one for interfacing with on-chip and off-chip user logic and register and the second interface is a direct interface to external asynchronous SRAM and synchronous BURST SRAM. The PowerPC slave works together with other devices or system controllers on the PowerPC bus. The slave can be assigned to a specific address space where it is mapped into. Access to the slave device is further directed to either the SRAM interface or the user interface bus based on address mapping. The address mapping controller can be hardwired to the core or can be supplied by the user during run-time. The slave supports both the regular data transfer size and also the extended data transfer size specific to MPC8260. The slave handles address pipeline on the PowerPC bus with up to 2 outstanding requests. While the slave is processing data transfer of one request, the CPU can start the address tenure of a second request. Address retry and separate address and data bus tenure are also supported by the slave. The slave detects data bus grant and data bus busy before starting its data tenure.
OPTIONAL FEATURES
The following table summarizes the optional features which can be provided with the core as required by user application. Options SRAM speed Pipeline or flow-through burst SRAM Bus sharing Data parity Multiple address mapping Description Different SRAM access speed can be programmed as wait states. Support both types of burst SRAM. Sharing the CPU bus with MPC106/107 Supports PowerPC data parity Address space mapping to support multiple user logic devices.
Actel Device Utilization Data
Family ProASICPlus Axcelerator RTSX-S
Device (-speed grade) APA150-STD AX500-3 RT54SX32S-2 SEQ 584 620 618
Utilization COMB 1566 534 548 Total 35% 15% 41% RAM
Performance 50Mhz 99Mhz 47Mhz
(c) 2003 by Eureka Technology Inc. 4962 El Camino Real, Los Altos, CA 94022, USA
Page 2
Tel: 1 650 960 3800 Fax: 1 650 960 3805 http://www.eurekatech.com

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